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1 file number 2758.4 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999 hsp43881 digital filter the hsp43881 is a video speed digital filter (df) designed to ef?ciently implement vector operations such as fir digital ?lters. it is comprised of eight ?lter cells cascaded internally and a shift and add output stage, all in a single integrated circuit. each ?lter cell contains a 8 x 8-bit multiplier, three decimation registers and a 26-bit accumulator. the output stage contains an additional 26-bit accumulator which can add the contents of any ?lter cell accumulator to the output stage accumulator shifted right by 8 bits. the hsp43881 has a maximum sample rate of 30mhz. the effective multiply accumulate (mac) rate is 240mhz. the hsp43881 df can be con?gured to process expanded coef?cient and word sizes. multiple dfs can be cascaded for larger ?lter lengths without degrading the sample rate or a single df can process larger ?lter lengths at less than 30mhz with multiple passes. the architecture permits processing ?lter lengths of over 1000 taps with the guarantee of no over?ows. in practice, most ?lter coef?cients are less than 1.0, making even larger ?lter lengths possible. the df provides for 8-bit unsigned or twos complement arithmetic, independently selectable for coef?cients and signal data. each df ?lter cell contains three resampling or decimation registers which permit output sample rate reduction at rates of 1 / 2 , 1 / 3 or 1 / 4 the input sample rate. these registers also provide the capability to perform 2-d operations such as matrix multiplication and n x n spatial correlations/convolutions for image processing applications. features ? eight filter cells ? 0mhz to 30mhz sample rate ? 8-bit coef?cients and signal data ? 26-bit accumulator per stage ? filter lengths over 1000 taps ? expandable coef?cient size, data size and filter length ? decimation by 2, 3 or 4 applications ? 1-d and 2-d fir filters ? radar/sonar ? adaptive filters ? echo cancellation ? complex multiply-add ? sample rate converters block diagram ordering information part number temp. range ( o c) package pkg. no. hsp43881jc-20 0 to 70 84 ld plcc n84.1.15 hsp43881jc-25 0 to 70 84 ld plcc n84.1.15 HSP43881JC-30 0 to 70 84 ld plcc n84.1.15 hsp43881gc-20 0 to 70 85 ld pga g85.a hsp43881gc-25 0 to 70 85 ld pga g85.a hsp43881gc-30 0 to 70 85 ld pga g85.a tcci cin0 - 7 df filter cell 7 erase dcmo - 1 dienb cienb coenb mux clk adr0 - 2 reset 26 adr0, adr1, adr2 clk reset shadd senbh senbl output stage 8 v cc v ss din0 - din7 tcs 3 df filter cell 6 26 8 8 df filter cell 5 26 8 8 df filter cell 4 26 8 8 df filter cell 3 26 8 8 df filter cell 2 26 8 8 df filter cell 1 26 8 8 df filter cell 0 26 8 8 8 5 5 2 26 2 8 5 tcco cout0 - 7 sum0 - 25 8 26 data sheet may 1999
2 pinouts 85 pin grid array (pga) top view, pins down hsp43881 top view, pins up a b c d e f g h j k l coenb reset din7 v cc din6 din3 din0 tcci v cc v cc cout7 erase din1 din2 cienb cin7 cin6 cin4 cout5 cout6 align pin dienb din5 din4 cin5 cin3 cin2 v cc cin1 cin0 senbl cout3 cout4 cout1 v ss cout2 v ss cout0 shadd adr2 dcm0 clk sum0 v cc v ss sum1 sum3 sum2 sum5 sum4 adr0 sum25 v cc sum7 v ss sum16 sum17 sum20 senbh sum24 v ss v cc sum19 v ss sum15 sum12 sum10 sum8 sum6 sum9 sum11 v ss sum13 v cc sum14 sum18 sum21 sum22 sum23 dcm1 2 17 3 4 5 6 8 9 10 11 v ss tcco tcs adr1 v ss dcm1 sum23 sum22 sum21 sum18 sum14 sum13 sum11 sum9 v ss v cc sum20 sum17 sum16 sum7 adr0 sum5 sum4 adr2 dcm0 clk v ss cout0 shadd sum1 sum3 sum2 sum0 v cc v ss cin2 v cc cout3 cout4 align pin a b c d e f g h j k l 1234 567 891011 adr1 sum25 v cc v ss v ss v cc v ss senbh sum24 sum19 sum15 sum12 sum10 sum8 sum6 cin1 cin0 senbl cout1 v ss cout2 cout5 cout6 dienb din5 din4 cin5 cin3 v cc v ss din0 din3 din6 din7 v ss coenb v cc reset cin8 v cc cin4 cin6 cin7 cienb din2 din1 erase cout7 din8 cout8 hsp43881
3 84 lead plcc package bottom view note: an overbar on a signal name represents an active low signal. pinouts (continued) v ss sum24 dcm1 sum25 senbh v cc addr0 addr1 v ss dcm0 addr2 clk shadd cout0 cout1 v ss cout2 111098765432184838281807978777675 cout3 cout4 v cc cout5 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 sum6 v ss sum5 sum4 v cc sum3 sum2 sum1 sum0 v ss senbl cin0 cin1 v cc cin2 cin3 cin4 cin5 v ss cin7 cin6 sum23 sum22 v cc sum21 sum20 sum19 sum18 v ss sum17 sum16 v cc sum15 sum14 sum13 sum12 v ss sum11 sum10 sum9 sum8 sum7 cout6 cout7 v ss tcco coenb v cc erase reset dienb tcs din7 din6 din5 din4 din3 din2 din1 din0 cienb tcci v cc hsp43881
4 pin description symbol pin number type description v cc a3, a10, b1, d11, f10, j1, k4, l7 +5v power supply input. v ss a1, a11, e2, f1, e11, h11, k3, k6, l9 power supply ground input. clk g3 i the clk input provides the df system sample clock. the maximum clock frequency is 30mhz. din0-7 a58, b67, c67 i these eight inputs are the data sample input bus. eight bit data samples are synchronously loaded through these pins to the x register of each ?lter cell simultaneously. the dienb signal enables loading, which is synchronous on the rising edge of the clock signal. tcs b5 i the tcs input determines the number system interpretation of the data input samples on pins din0-7 as follows: tcs = low ? unsigned arithmetic. tcs = high ? two's complement arithmetic. the tcs signal is synchronously loaded into the x register in the same way as the din0-7 inputs. dienb c5 i a low on this enables the data sample input bus (din0-7) to all the ?lter cells. a rising edge of the clk signal occurring while dienb is low will load the x register of every ?lter cell with the 8-bit value present on din0-7. a high on this input forces all the bits of the data sample input bus to zero; a rising clk edge when dienb is high will load the x register of every ?lter cell with all zeros. this signal is latched inside the df, delaying its effect by one clock internal to the df. therefore, it must be low during the clock cycle immediately preceding presentation of the desired data on the din0-7 inputs. detailed operation is shown in later timing diagrams. cin0-7 b9-11, c10-11, d10, e9-10 i these eight inputs are used to input the 8-bit coef?cients. the coef?cients are synchronously load- ed into the c register of ?lter cell 0 if a rising edge of clk occurs while cienb is low. the cienb signal is delayed by one clock as discussed below. tcci a9 i the tcci input determines the number system interpretation of the coef?cient inputs on pins cin07 as follows: tcci = low e unsigned arithmetic. tcci = high e two's complement arithmetic. the tcci signal is synchronously loaded into the c register in the same way as the cin0-7 inputs. cienb b8 i a low on this input enable the c register of every ?lter cell and the d registers (decimation) of every ?lter cell according to the state of the dcm0-1 inputs. a rising edge of the clk signal occurring while cienb is low will load the c register and appropriate d registers with the coef?cient data present at their inputs. this provides the mechanism for shifting the coef?cients from cell to cell through the device. a high on this input freezes the contents of the c register and the d registers ignoring the clk signal. this signal is latched and delayed by one clock internal to the df. therefore, it must be low during the clock cycle immediately preceding presentation of the desired coef?cient of the cin0- 7 inputs. detailed operation is shown in the timing diagrams section. cout0-7 b2, c1-2, d1-2, e1, e3, f2 o these eight three-state outputs are used to output the 8-bit coef?cients from ?lter cell 7. these out- puts are enabled by the coenb signal low. these outputs may be tied to the cin0-7 inputs of the same df to recirculate the coef?cients, or they may be tied to the cin0-7 inputs of another df to cascade dfs for longer ?lter lengths. tcco b3 o the tcco three-state output determines the number system representation of the coef?cients out- put on couto-7. it tracks the tcci signal to this same df. it should be tied to the tcci input of the next df in a cascade of dfs for increased ?lter lengths. this signal is enabled by coenb low. coenb a2 i a low on the coenb input enables the cout0-7 and the tcco output. a high on this input places all these outputs in their high impedance state. hsp43881
5 functional description the digital filter processor (df) is composed of eight filter cells cascaded together and an output stage for combining or selecting filte5r cell outputs (see block diagram). each filter cell contains a multiplier accumulator and several registers (figure 1). each 8-bit coefficient is multiplied by an 8-bit data sample, with the result added to the 26-bit accumulator contents. the coefficient output of each cell is cascaded to the coefficient input of the next cell to its right. df filter cell an 8-bit coefficient (cin0-7) enters each cell through the c register on the left and exits the cell on the right as signals cout0-7. with no decimation, the coefficient moves directly from the c register to the output, and is valid on the clock following its entrance. when decimation is selected the coefficient exit is delayed by 1, 2 or 3 clocks by passing through one or more decimation registers (d1, d2 or d3). the combination of d registers through which the coefficient passes is determined by the state of dcm0 and dcm1. the output signals (cout0-7) are connected to the cin0-7 inputs of the next cell to its right. the coenb input signal enables the cout0-7 outputs of the right most cell to the cout-07 pins of the device. the c and d registers are enabled for loading by cienb. loading is synchronous with clk when cienb is low. note that dcm0-1 g2, l1 these two inputs determine the use of the internal decimation registers as follows: dcm1 dcm0 decimation function 0 0 decimation registers not used. 0 1 one decimation register is used. 1 0 two decimation registers are used. 1 1 three decimation registers are used. the coef?cients pass from cell to cell at a rate determined by the number of decimation registers used. when no decimation registers are used, coef?cients move from cell to cell on each clock. when one decimation register is used, coef?cients move from cell to cell on every other clock, etc. these signals are latched and delayed by one clock internal to the df. sum0-25 j2, j5-8, j10, k2, k5-11, l-26, l8, l10-11 o these 26 three-state outputs are used to output the results of the internal ?lter cell computations. individual ?lter cell results or the result of the shift and add output stage can be output. if an individ- ual ?lter cell result is to be output, the adr0-2 signals select the ?lter cell result. the shadd signal determines whether the selected ?lter cell result or the output stage adder result is output. the sig- nals senbh and senbl enable the most signi?cant and least signi?cant bits of the sum0-25 result, respectively. both senbh and senbl may be enabled simultaneously if the system has a 26-bit or larger bus. however, individual enables are provided to facilitate use with a 16-bit bus. senbh k1 i a low on this input enables result bits sum16-25. a high on this input places these bits in their high impedance state. senbl e11 i a low on this input enables result bits sum0-15. a high on this input places these bits in their high impedance state. adr0-2 g1, h1-2 i these inputs select the one cell whose accumulator will be read through the output bus (sum0-25) or added to the output stage accumulator. they also determine which accumulator will be cleared when erase is low. for selection of which accumulator to read through the output bus (sum0-25) or which to add to the output stage accumulator, these inputs are latched in the df and delayed by one clock internal to the device. if the adr0-2 lines remain at the same address for more than one clock, the output at sum0-25 will not change to re?ect any subsequent accumulator updates in the addressed cell. only the result available during the ?rst clock, when adr0-1 selects the cell, will be output. this does not hinder normal operation since the adr0-1 lines are changed sequentially. this feature facilitates the interface with slow memories where the output is required to be ?xed for more than one clock. shadd f3 i the shadd input controls the activation of the shift-and-add operation in the output stage. this signal is latched in the df and delayed by one clock internal to the device. a detailed explanation is given in the df output stage section. reset a4 i a low on this input synchronously clears all the internal registers, except the cell accumulators. it can be used with erase to also clear all the accumulators simultaneously. this signal is latched in the df and delayed by one clock internal to the df. erase b4 i a low on this input synchronously clears the cell accumulator selected by the adr0-1 signals. if reset is also low simultaneously, all cell accumulators are cleared. align pin c3 used for aligning chip in socket or printed circuit board. must be left as a no connect in circuit. pin description (continued) symbol pin number type description hsp43881
6 cienb is latched internally. it enables the register for loading after the next clk following the onset of cienb low. actual loading occurs on the second clk following the onset of cienb low. therefore, cienb must be low during the clock cycle immediately preceding presentation of the coefficient on the cin0-7 inputs. in most basic fir operations, cienb will be low throughout the process, so this latching and delay sequence is only important during the initialization phase. when cienb is high, the coefficients are frozen. these registers are cleared synchronously under control of reset, which is latched and delayed exactly like cienb. the output of the c register (c0-8) is one input to 8 x 8 multiplier. the other input to the 8 x 8 multiplier comes from the output of the x register. this register is loaded with a data sample from the device input signals din0-7 discussed above. the x register is enabled for loading by dienb. loading is synchronous with clk when dienb is low. note that dienb is latched internally. it enables the register for loading after the next clk following the onset of dienb low. actual loading occurs on the second clk following the onset of dienb low; therefore, dienb must be low during the clock cycle immediately preceding presentation of the data sample on the din0-7 inputs. in most basic fir operations, dienb will be low throughout the process, so this latching and delay sequence is only important during the initialization phase. when dienb is high, the x register is loaded with all zeros. the multiplier is pipelined and is modeled as a multiplier core followed by two pipeline registers, mreg0 and mreg1 (figure 1). the multiplier output is sign extended and input as one operand of the 26-bit adder. the other adder operand is the output of the 26-bit accumulator. the adder output is loaded synchronously into both the accumulator and the treg. the treg loading is disabled by the cell select signal, celln, where n is the cell number. the cell select is decoded from the adr0-2 signals to generate the treg load enable. the cell select is inverted and applied as the load enable to the treg. operation is such that the treg is loaded whenever the cell is not selected. therefore, treg is loaded every clock except the clock following cell selection. the purpose of the treg is to hold the result of a sum of products calculation during the clock when the accumulator is cleared to prepare for the next sum of products calculation. this allows continuous accumulation without wasting clocks. the accumulator is loaded with the adder output every clock unless it is cleared. it is cleared synchronously in two ways. when reset and erase are both low, the accumulator is cleared along with all other registers on the device. since erase and reset are latched and delayed one clock internally, clearing occurs on the second clk following the onset of both erase and reset low. the second accumulator clearing mechanism clears a single accumulator in a selected cell. the cell select signal, celln, decoded from adr0-2 and the erase signal enable clearing of the accumulator on the next clk. the erase and reset signals clear the df internal registers and states as follows: the df output stage the output stage consists of a 26-bit adder, 26-bit register, feedback multiplexer from the register to the adder, an output multiplexer and a 26-bit three-state driver stage (figure 2). the 26-bit output adder can add any filter cell accumulator result to the 18 most significant bits of the output buffer. this result is stored back in the output buffer. this operation takes place in one clock period. the eight lsbs of the output buffer are lost. the filter cell accumulator is selected by the adr0-2 inputs. the 18 msbs of the output buffer actually pass through the zero mux on their way to the output adder input. the zero mux is controlled by the shadd input signal and selects either the output buffer 18 msbs or all zeros for the adder input. a low on the shadd input selects zero. a high on the shadd input selects the output buffer msbs, thus, activating the shift and add operation. the shadd signal is latched and delayed by one clock internally. erase reset clearing effect 1 1 no clearing occurs, internal state remains same. 10 reset only active, all registers except accu- mulators are cleared, including the internal pipeline registers. 01 erase only active, the accumulator whose address is given by the adr0-2 inputs is cleared. 0 0 both reset and erase active, all accumula- tors, as well as all other registers are cleared. hsp43881
7 dcm1.d reset .d dcm0.d cienb.d tcci cin0-7 7 reset .d dienb.d tcs din0-7 0 clk c0-7 0-7 ld clr d1 reg clk 1 c0-8 mux d0-7 d.tcci ld clr d2 reg clk ld clr d3 reg 0 1 mux tcco cout0-7 three-state buffers on cell 7 only coenb multiplier core c x p0-17 x0-8 reset .d mreg0 clr clk ld clr x reg mreg1 clr adder 0-17 sign extension 18-25 acc clr ld t reg aout0-25 erase.d celln celln adr2 adr1 adr0 cell 0 cell 1 cell 7 clk erase adr2 adr1 adr0 cienb dienb reset dcm0 dcm1 latches ld clr c reg acc0-25 clk decoder 7 b c.tcci figure 1. filter cell clk erase.d adr2.d adr1.d adr0.d cienb.d dienb.d reset.d dcm0.d dcm1.d d q clk acc.d0-25 hsp43881
8 the 26 least signi?cant bits (lsbs) from either a cell accumulator or the output buffer are output on the sum0-25 bus. the output mux determines whether the cell accumulator selected by adr0-2 or the output buffer is output to the bus. this mux is controlled by the shadd input signal. control is based on the state of the shadd during two successive clocks; in other words, the output mux selection contains memory. if shadd is low during a clock cycle and was low during the previous clock, the output mux selects the contents of the ?lter cell accumulator addressed by adr0-2. otherwise the output mux selects the contents of the output buffer. if the adr0-2 lines remain at the same address for more than one clock, the output at sum0-25 will not change to re?ect any subsequent accumulator updates in the addressed cell. only the result available during the ?rst clock when adr0-2 selects the cell will be output. this does not hinder normal fir operation since the adr0-2 lines are changed sequentially. this feature facilitates the interface with slow memories where the output is required to be ?xed for more than one clock. the sum0-25 output bus is controlled by the senbh and senbl signals. a low on senbl enables bits sum0-15. a low on senbh enables bits sum16-25. thus, all 26 bits can be output simultaneously if the external system has a 26-bit or larger bus. if the external system bus is only 16 bits, the bits can be enabled in two groups of 16 and 10 bits (sign extended). df arithmetic both data samples and coef?cients can be represented as either unsigned or two's complement numbers. the tcs and tcci inputs determine the type of arithmetic representation. internally all values are represented by a 9-bit two's complement number. the value of the additional ninth bit depends on the arithmetic representation selected. for two's complement arithmetic, the sign is extended into the ninth bit. for unsigned arithmetic, bit-9 is 0. the multiplier output is 18 bits and the accumulator is 26 bits. the accumulator width determines the maximum possible number of terms in the sum of products without mux cell result 18 (lsbs) reset .d output 18 clr d 26 26 26 26 01 67 3 26 buffer output mux three-state buffer zero mux 01 0 18 msbs shifted 8 bits to right 8-25 clk q clr dq clk 26 26 26 clk 26 sum0-25 shadd senbl senbh 2 shadd.d 0-17 sign ext 0-18 reset .d reset .d 0 1 8 adr0.d-adr2.d 18 18-25 26 + figure 2. df output stage (bits 0 - 17) hsp43881
9 over?ow. the maximum number of terms depends also on the number system and the distribution of the coef?cient and data values. then maximum numbers of terms in the sum products are: for practical fir ?lters, the coef?cients are never all near maximum value, so even larger vectors are possible in practice. basic fir operation a simple, 30mhz 8-tap ?lter example serves to illustrate more clearly the operation of the df. the sequence table (table 1) shows the results of the multiply accumulate in each cell after each clock. the coef?cient sequence, cn, enters the df on the left and moves from left to right through the cells. the data sample sequence, xn, enters the df from the top, with each cell receiving the same sample simultaneously. each cell accumulates the sum of products for one output point. eight sums of products are calculated simultaneously, but staggered in time so that a new output is available every system clock. number system max # of terms two unsigned vectors 1032 two two's complement: ? two positive vectors ? negative vectors ? one positive and one negative vector 2080 2047 2064 one unsigned and one two's complement vector: ? positive two's complement vector ? negative two's complement vector 1036 1028 table 1. 30mhz, 8-tap fir filter sequence clk cell 0 cell 1 cell 2 cell 3 cell 4 cell 5 cell 6 cell 7 sum/clr 0c 7 x x 0 000 - 1+c 6 x x 1 c 7 x x 1 00 - 2+c 5 x x 2 +c 6 x x 2 c 7 x x 2 0- 3+c 4 x x 3 +c 5 x x 3 +c 6 x x 3 c 7 x x 3 - 4+c 3 x x 4 +c 4 x x 4 +c 5 x x 4 +c 6 x x 4 c 7 x x 4 - 5+c 2 x x 5 c 3 x x 5 +c 4 x x 5 +c 5 x x 5 +c 6 x x 5 c 7 x x 5 - 6+c 1 x x 6 +c 2 x x 6 +c 3 x x 6 +c 4 x x 6 +c 5 x x 6 +c 6 x x 6 c 7 x x 6 - 7+c 0 x x 7 +c 1 x x 7 +c 2 x x 7 +c 3 x x 7 +c 4 x x 7 +c 5 x x 7 +c 6 x x 7 c 7 x x 7 cell 0 (y7) 8c 7 x x 8 +c 0 x x 8 +c 1 x x 8 +c 2 x x 8 +c 3 x x 8 +c 4 x x 8 +c 5 x x 8 +c 6 x x 8 cell 1 (y8) 9+c 6 x x 9 c 7 x x 9 +c 0 x x 9 +c 1 x x 9 +c 2 x x 9 +c 3 x x 9 +c 4 x x 9 +c 5 x x 9 cell 2 (y9) 10 +c 5 x x 10 +c 6 x x 10 c 7 x x 10 +c 0 x x 10 +c 1 x x 10 +c 2 x x 10 +c 3 x x 10 +c 4 x x 10 cell 3 (y10) 11 +c 4 x x 11 +c 5 x x 11 +c 6 x x 11 c 7 x x 11 +c 0 x x 11 +c 1 x x 11 +c 2 x x 11 +c 3 x x 11 cell 4 (y11) 12 +c 3 x x 12 +c 4 x x 12 +c 5 x x 12 +c 6 x x 12 c 7 x x 12 +c 0 x x 12 +c 1 x x 12 +c 2 x x 12 cell 5 (y12) 13 +c 2 x x 13 +c 3 x x 13 +c 4 x x 13 +c 5 x x 13 +c 6 x x 13 c 7 x x 13 +c 0 x x 13 +c 1 x x 13 cell 6 (y13) 14 +c 1 x x 14 +c 2 x x 14 +c 3 x x 14 +c 4 x x 14 +c 5 x x 14 +c 6 x x 14 +c 7 x x 14 +c 0 x x 14 cell 7 (y14) 15 +c 0 x x 15 +c 1 x x 15 +c 2 x x 15 +c 3 x x 15 +c 4 x x 15 +c 5 x x 15 +c 6 x x 15 c 7 x x 15 cell 0 (y15) x 15 ...x 9, x 8, x 7 ...x 1, x 0 c 0 ...c 6, c 7, c 0 ...c 6, c 7 hsp43881 y 15 ...y 14, ...y 8, y 7 hsp43881
10 detailed operation of the df to perform a basic 8-tap, 8-bit coef?cient, 8-bit data, 30mhz fir ?lter is best understood by observing the schematic (figure 3) and timing diagram (figure 4). the internal pipeline length of the df is four (4) clock cycles, corresponding to the register levels creg (or xreg), mreg0, mreg1, and treg (figures 1 and 2). therefore, the delay from presentation of data and coef?cients at the din0-7 and cin0-7 inputs to a sum appearing at the sum0-25 output is: k + td where: k = ?lter length td = 4, the internal pipeline delay of df after the pipeline has ?lled, a new output sample is available every clock. the delay to last sample output from last sample input is td. the output sums, yn, shown in the timing diagram are derived from the sum of products equation: y(n) = c(0) x x(n) + c(1) x x(n1) + c(2) x x(n -2) + c(3) x x(n -3) + c(4) x x(n -4) + c(5) x x(n -5) + c(6) x x(n -6) + c(7) x x(n -7) extended fir filter length filter lengths greater that eight taps can be created by either cascading together multiple df devices or reusing a single device. using multiple devices, an fir ?lter of over 1000- taps can be constructed to operate at a 30mhz sample rate. using a single device clocked at 30mhz, a fir ?lter of over 1000 taps can be constructed to operate at less than a 30mhz sample rate. combinations of these two techniques are also possible. sample data in (x n ) 30mhz clock 3-bit counter y 2 y 1 y 0 a2 a1 a0 d0-d7 8 x 8 coeff. ram/rom system reset erase +5v sum0-25 26 sum out (y n ) nc nc 8 tcco cout0-7 coenb v ss erase reset dcm0 dcm1 cienb cin0-7 tcci clk tcs dienb din0-7 hsp43881 8 8 senbl senbh shadd v cc adr0 adr1 adr2 figure 3. 30mhz, 8 tap fir filter application schematic hsp43881
11 01234567 9 8 1011121314151617181920 x 18 x 17 x 16 x 15 x 14 x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 c 7 c 6 c 5 0 7 6 5 4 3 2 1 0 y 7 y 8 y 9 y 10 y 11 y 12 y 13 y 14 dcm0-1 senbh senbl shadd sum0-24 adr0-2 cienb cin0-7 dienb din0-7 erase reset clk 0 y n c k x nk C k0 = 7 ? = figure 4. 30mhz, 8-tap fir filter timing hsp43881
12 sample data in (x n ) 30mhz clock c d q d0-d7 8x16 coeff. ram/rom system reset +5v a1 a2 a3 nc nc 8 tcco cout0-7 coenb v ss erase reset dcm0 dcm1 cienb cin0-7 tcci clk tcs dienb din0-7 hsp43881 8 8 senbl senbh shadd v cc adr2 adr0 adr1 +5v sum0-24 25 8 tcco cout0-7 coenb v ss erase reset dcm0 dcm1 cienb cin0-7 tcci clk tcs dienb din0-7 8 senbl senbh shadd v cc adr2 adr0 adr1 sum0-24 25 df1 sum out (y n ) a0 4-bit clk y1 y2 y3 y0 counter reset q hsp43881 df0 figure 5. 30mhz, 16-tap fir filter cascade application schematic hsp43881
13 cascade con?guration to design a ?lter length l>8, l/8 dfs are cascaded by connecting the cout0-7 outputs of the (i)th df to the cin0- 7 inputs of the (i+1)th df. the din0-7 inputs and sum0-25 outputs of all the dfs are also tied together. a speci?c example of two cascaded dfs illustrates the technique (figure 5). timing (figure 6) is similar to the simple 8-tap fir, except the erase and senbl/ senbh signals must be enabled independently for the two dfs in order to clear the correct accumulators and enable the sum0-25 output signals at the proper times. single df con?guration using a single df, a ?lter of length l>8 can be constructed by processing in l/8 passes as illustrated in the following table (table 2) for a 16-tap fir. each pass is composed of tp = 7 + l cycles and computes eight output samples. in pass i, the sample with indices i*8 to i*8 +(l1) enter the din0-7 inputs. the coef?cients c 0 -c l-1 enter the cin0-7 inputs, followed by seven zeros. as these zeros are entered, the result samples are output and the accumulators reset. initial ?ling of the pipeline is not shown in this sequence table. filter outputs can be put through a fifo to even out the sample rate. extended coef?cient and data sample word size the sample and coef?cient word size can be extended by utilizing several dfs in parallel to get the maximum sample rate or a single df with resulting lower sample rates. the technique is to compute partial products of 8 x 8 and combine these partial products by shifting and adding to obtain the ?nal result. the shifting and adding can be accomplished with external adders (at full speed) or with the df's shift and add mechanism contained in its output stage (at reduced speed). decimation/resampling the hsp43881 df provides a mechanism for decimating by factors of 2, 3, or 4. from the df ?lter cell block diagram (figure 1), note the three d registers and two multiplexers in the coef?cient path through the cell. these allow the coef?cients to be delayed by 1, 2, or 3 clocks through the cell. the sequence table (table 3) for a decimate by two ?lter illustrates the technique (internal cell pipelining ignored for simplicity). detailed timing for a 30mhz input sample rate, 15mhz output sample rate (i.e., decimate by two), 16-tap fir ?lter, including pipelining, is shown in figure 7. this ?lter requires only a single hsp43881 df. hsp43881
14 clk reset df0 erase df1 erase din0-7 dienb cin0-7 cienb adr0-2 df0 sum0-25 df1 sum0-25 shadd df0 senbl/h df1 senbl/h dcm0-1 22 23 24 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 x 9 x 10 x 11 x 12 x 13 x 14 x 15 x 16 x 17 x 18 x 19 x 20 x 21 x 22 x 23 x 24 x 25 x 26 x 27 x 28 x 29 x 30 x 31 x 32 x 33 x 34 x 35 x 36 x 37 c 15 c 14 c 13 c 12 c 11 c 10 c 9 c 8 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 c 15 c 14 c 13 c 12 c 11 c 10 c 9 c 8 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 c 15 c 14 c 13 c 12 c 11 c 10 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 3 y 33 y 32 y 31 2 1 0 y 30 y 29 7 6 y 28 y 27 5 4 y 26 y 25 3 2 y 24 y 23 1 0 y 22 y 21 7 6 y 20 y 19 5 4 y 18 y 17 3 2 y 16 y 15 1 0 0 y n c k x nk C k0 = 15 ? = figure 6. 16-tap 30mhz fir filter timing using two cascaded hsp43881s hsp43881
15 table 2. 16-tap fir filter sequence using a single df clk cell 0 cell 1 cell 2 cell 3 cell 4 cell 5 cell 6 cell 7 sum/clr 6c 15 x x 0 000 - 7+c 14 x x 1 c 15 x x 1 +c 0 x x 16 00 - 8+c 13 x x 2 c 15 x x 2 c 0 x x 17 0- 9+c 12 x x 3 c 15 x x 3 - 10 +c 11 x x 4 +c 14 x x 4 c 15 x x 4 c 0 x x 19 - 11 +c 10 x x 5 +c 13 x x 5 c 15 x x 5 c 0 x x 20 - 12 +c 9 x x 6 +c 12 x x 6 c 15 x x 6 c 0 x x 21 - 13 +c 8 x x 7 +c 11 x x 7 c 15 x x 7 - 14 +c 7 x x 8 +c 10 x x 8 c 14 x x 8 - 15 +c 6 x x 9 +c9 x x 9 c 13 x x 9 - 16 +c 5 x x 10 +c 8 x x 10 c 12 x x 10 - 17 +c 4 x x 11 +c 7 x x 11 c 11 x x 11 - 18 +c 3 x x 12 +c 6 x x 12 c 10 x x 12 - 19 +c 2 x x 13 +c 5 x x 13 c 9 x x 13 - 20 +c 1 x x 14 +c 4 x x 14 c 8 x x 14 - 21 +c 0 x x 15 +c 3 x x 15 c 7 x x 15 cell 0 (y15) 22 0 +c 2 x x 16 c 6 x x 16 cell 1 (y16) 23 0 0 +c 1 x x 17 c 5 x x 17 cell 2 (y17) 24 0 0 0 +c 0 x x 18 c 4 x x 18 cell 3 (y18) 250000 c 3 x x 19 cell 4 (y19) 26000 0 0c 2 x x 20 cell 5 (y20) 27000 0 00 c 1 x x 21 cell 6 (y21) 28000 0 000c 0 x x 22 cell 7 (y22) data sequence input x 30 ...x 9 , x 8, x 22 ...x 1, x 0 coef?cient sequence input c 0 ...c 14 , c 15, 0...0, c 0 ...c 14, c 15 hsp43881 ...0, y 30 ...y 23, 0...0, y 22, ...y 15, 0...0 hsp43881
16 29 c 15 x x 80 0 0 0000 - 30 +c 14 x x 9 c 15 x x 9 c 0 x x 24 0 0 0000 - 31 +c 13 x x 10 +c 15 x x 10 c 0 x x 25 00000 - 32 +c 12 x x 11 c 0 x x 26 0000 - 33 +c 11 x x 12 c 15 x x 12 000 - 34 +c 10 x x 13 c 15 x x 13 00 - 35 +c 9 x x 14 c 15 x x 14 0- 36 +c 8 x x 15 c 15 x x 15 - 37 +c 7 x x 16 c 14 x x 16 - 38 +c 6 x x 17 c 13 x x 17 - 39 +c 5 x x 18 c 12 x x 18 - 40 +c 4 x x 19 c 11 x x 19 - 41 +c 3 x x 20 c 10 x x 20 - 42 +c 2 x x 21 c 9 x x 21 - 43 +c 1 x x 22 c 8 x x 22 - 44 +c 0 x x 23 c 7 x x 23 cell 0 (y23) 45 0 c 6 x x 24 cell 1 (y24) 46 0 0 c 5 x x 25 cell 2 (y25) 47000 c 4 x x 26 cell 3 (y26) 48000 c 0 x x 27 c 3 x x 27 cell 4 (y27) table 2. 16-tap fir filter sequence using a single df (continued) clk cell 0 cell 1 cell 2 cell 3 cell 4 cell 5 cell 6 cell 7 sum/clr data sequence input x 30 ...x 9 , x 8, x 22 ...x 1, x 0 coef?cient sequence input c 0 ...c 14 , c 15, 0...0, c 0 ...c 14, c 15 hsp43881 ...0, y 30 ...y 23, 0...0, y 22, ...y 15, 0...0 hsp43881
17 table 3. 16-tap decimate by two fir filter sequence; 30mhz in, 15mhz out clk cell 0 cell 1 cell 2 cell 3 cell 4 cell 5 cell 6 cell 7 sum/clr 6c 15 x x 0 0000000 - 7+c 14 x x 1 0000000 - 8+c 13 x x 2 c 15 x x 2 +c 14 x x 31 000000 - 9+c 12 x x 3 000000 - 10 +c 11 x x 4 c 15 x x 4 +c 14 x x 31 00000 - 11 +c 10 x x 5 00000 - 12 +c 9 x x 6 c 15 x x 6 +c 14 x x 31 000 0 - 13 +c 8 x x 7 000 0 - 14 +c 7 x x 8 c 15 x x 8 +c 14 x x 31 00 0 - 15 +c 6 x x 9 00 0 - 16 +c 5 x x 10 c 15 x x 10 +c 14 x x 31 00 - 17 +c 4 x x 11 00 - 18 +c 3 x x 12 c 15 x x 12 +c 14 x x 31 0- 19 +c 2 x x 13 0- 20 +c 1 x x 14 c 15 x x 14 - 21 +c 0 x x 15 +c 14 x x 15 cell 0 (y15) 22 c 15 x x 16 +c 13 x x 16 - 23 +c 14 x x 17 +c 12 x x 17 cell 1 (y17) 24 +c 13 x x 18 +c 11 x x 18 - 25 +c 12 x x 19 +c 10 x x 19 cell 2 (y19) 26 +c 11 x x 20 +c 9 x x 20 - 27 +c 10 x x 21 +c 8 x x 21 cell 3 (y21) 28 +c 9 x x 22 +c 7 x x 22 - 29 +c 8 x x 23 +c 6 x x 23 cell 4 (y23) 30 +c 7 x x 24 +c 5 x x 24 - 31 +c 6 x x 25 +c 4 x x 25 cell 5 (y25) 32 +c 5 x x 26 +c 3 x x 26 - 33 +c 4 x x 27 +c 2 x x 27 cell 6 (y27) 34 +c 3 x x 28 +c 1 x x 28 - 35 +c 2 x x 29 +c 0 x x 29 cell 7 (y29) 36 +c 1 x x 30 c 15 x x 30 - 37 +c 0 x x 31 +c 14 x x 31 cell 8 (y31) data sequence input ...x 2 , x 1, x 0 coef?cient sequence input ...c 15 , c 0 , ...c 13, c 14 , c 15 hsp43881 ...y 19 , -, ...y 17, -, y 15 hsp43881
18 clk dcm0-1 22 23 24 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 x 9 x 10 x 11 x 12 x 13 x 14 x 15 x 16 x 17 x 18 x 19 x 20 x 21 x 22 x 23 x 24 x 25 x 26 x 27 x 28 x 29 x 30 x 31 x 32 x 33 x 34 x 35 x 36 x 37 c 15 c 14 c 13 c 12 c 11 c 10 c 9 c 8 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 c 15 c 14 c 13 c 12 c 11 c 10 c 9 c 8 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 c 15 c 14 c 13 c 12 c 11 c 10 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 y 33 y 31 y 29 y 27 y 25 y 23 y 21 y 19 y 17 y 15 1 0 1 23456701 reset erase din0-7 dienb cin0-7 cienb adr0-2 sum0-25 shadd senbl senbh figure 7. 16-tap decimate-by-two fir filter timing; 30mhz, 15mhz out hsp43881
19 absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0v input, output voltage . . . . . . . . . . . . . . . . . . . gnd -0.5 to v cc 0.5v esd rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating conditions voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v 5% temperature range . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c thermal resistance (typical, note 1) q ja ( o c/w) q jc ( o c/w) plcc package . . . . . . . . . . . . . . . . . . 34 n/a pga package . . . . . . . . . . . . . . . . . . . 36 7 maximum junction temperature plcc pac kage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 o c pga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 o c maximum storage t emperature range . . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (plcc - lead tips only) die characteristics gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17,763 gates caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio nofthe device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied. note: 1. q ja is measured with the component mounted on an evaluation pc board in free air. dc electrical speci?cations parameter symbol notes test conditions min max units power supply current i ccop notes 2, 4 v cc = max clk frequency 20mhz - 140 ma standby power supply current i ccsb note 4 v cc = max - 500 m a input leakage current i i v cc = max, input = 0v or v cc -10 10 m a output leakage current i o v cc = max, input = 0v or v cc -10 10 m a logical one input voltage v ih v cc = max 2.0 - v logical zero input voltage v il v cc = min - 0.8 v logical one output voltage v oh i oh = 400 m a, v cc = min 2.6 - v logical zero output voltage v ol i ol = 2ma, v cc = min - 0.4 v clock input high v ihc v cc = max 3.0 - v clock input low v ilc v cc = min - 0.8 v input capacitance plcc pga c in note 3 clk frequency 1mhz all measurements referenced to gnd t a = 25 o c -10 15 pf pf output capacitance plcc pga c out -10 15 pf pf notes: 2. operating supply current is proportional to frequency. typical rating is 7ma/mhz. 3. controlled via design or process parameters and not directly tested. characterized upon initial design and after major process and/or design changes. 4. output load per test load circuit and c l = 40pf. hsp43881
20 test load circuit ac electrical speci?cations v cc = 5v 5%, t a = 0 o c to + 70 o c parameter test conditions symbol notes -20 (20mhz) -25 (25.6mhz) -30 (30mhz) min max min max min max units clock period t cp 50 -39-33- ns clock low t cl 20 -16-13- ns clock high t ch 20 -16-13- ns input setup t is 16 -14-13- ns input hold t ih 0 -0-0- ns clk to coefficient output delay t odc - 24-20-18 ns output enable delay t oed - 20-15-15 ns output disable delay t odd note 5 - 20 - 15 - 15 ns clk to sum output delay t ods - 27-25-21 ns output rise t or note 5 - 6 -6-6 ns output fall t of note 5 - 6 -6-6 ns note: 5. controlled by design or process parameters and not directly tested. characterized upon initial design and after major process and/or design changes. dut equivalent circuit 1.5v i ol i oh (note 6) c l s 1 notes: 6. includes stray and jig capacitance. 7. switch s 1 open for i ccsb and i ccop tests. hsp43881
21 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?ce headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (407) 724-7000 fax: (407) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 waveforms figure 8. clock ac parameters ? input includes: din0-7, cin0-7, dienb, cienb, erase, reset,dcm0-1, adro-2, tcs, tcci, shadd figure 9. input setup and hold ? sum-25, couto-7, tcco are assumed not to be in high- impedance state. figure 10. sum0-25, cout0-7, tcco output delays figure 11. output rise and fall times figure 12. output enable, disable timing note: ac testing: inputs are driven at 3.0v for logic and 1 and 0.0v for logic 0. input and output timing measurements are made at 1.5 for both a logic 1 and 0. clk is driven at 4.0 and 0v and measured at 2.0v. figure 13. ac testing input, output waveform clk 2.0v 2.0v 2.0v t cp t ch t cl 0.0v clk 2.0v input ? 1.5v 1.5v 3.0v 0.0v 4.0v t is t ih clk sum0-25 cout0-7 tcco 2.0v 1.5v t odc, t ods 2.0v 0.8v t or t of high impedance 1.5v 1.7v 1.3v high impedance 1.5v sum0-25 cout0-7 tcco senbl senbh coenb t odd t oed 1.5v 3.0v 0.0v input 1.5v device under test output hsp43881

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